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Scalable NoC-based Programmable Cluster Architecture for future AI applications

ABG-127503 Sujet de Thèse
10/12/2024 Contrat doctoral
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CEA
Palaiseau - Ile-de-France - France
Scalable NoC-based Programmable Cluster Architecture for future AI applications
  • Sciences de l’ingénieur
  • Electronique
  • Informatique
Artificial Intelligence, Network-on-Chip, Programmable Cluster, Flexibility, Scalability

Description du sujet

 

Context

Artificial Intelligence (AI) has emerged as a major field impacting various sectors, including healthcare, automotive, robotics, and more. Hardware architectures must now meet increasingly demanding requirements in terms of computational power, low latency, and flexibility. Network-on-Chip (NoC) technology is a key enabler in addressing these challenges, providing efficient and scalable interconnections within multiprocessor systems. However, despite its benefits, designing NoCs poses significant challenges, particularly in optimizing latency, energy consumption, and scalability.

Programmable cluster architectures hold great promise for AI as they enable resource adaptation to meet the specific needs of deep learning algorithms and other compute-intensive AI applications. By combining the modularity of clusters with the advantages of NoCs, it becomes possible to design systems capable of handling ever-increasing AI workloads while ensuring maximum energy efficiency and flexibility.

 

Summary of the Thesis Topic

This PhD project aims to design a scalable, programmable cluster architecture based on a Network-on-Chip tailored for future AI applications. The primary objective will be to design and optimize a NoC architecture capable of meeting the high demands of AI applications in terms of intensive computing and efficient data transfer between processing clusters.

The research will focus on the following key areas:

  1. NoC Architecture Design: Developing a scalable and programmable NoC to effectively connect various AI processing clusters.
  2. Performance and Energy Efficiency Optimization: Defining mechanisms to optimize system latency and energy consumption based on the nature of AI workloads.
  3. Cluster Flexibility and Programmability: Proposing a modular and programmable architecture that dynamically allocates resources based on the specific needs of each AI application.
  4. Experimental Evaluation: Implementing and testing prototypes of the proposed architecture to validate its performance on real-world use cases, such as image classification, object detection, and real-time data processing.

The outcomes of this research may contribute to the development of cutting-edge embedded systems and AI solutions optimized for the next generation of AI applications and algorithms.

The work performed during this thesis will be presented at international conferences and scientific journals. Certain results may be patented.

 

Prise de fonction :

01/10/2025

Nature du financement

Contrat doctoral

Précisions sur le financement

Présentation établissement et labo d'accueil

CEA

About the CEA and LIST

This thesis will be hosted in the LECA Laboratory from CEA, in the DRT/LIST/DSCIN division.

The CEA (French Commission for Atomic and Renewable Energy) is a public research institute. It plays an important role in the research, development and innovation community. The CEA has four missions: security and defense, nuclear energy (fission and fusion), technology research for industry and fundamental research. With 16 000 employees, including technicians, engineers, researchers and support personnel, the CEA is involved in numerous research projects in collaboration with both academic and industrial partners.

In the section of the CEA focused on technology research for industry, the LIST institute is focused on intelligent digital systems. This institute has a culture of innovation and has as a mission to transfer these technologies to industrial partners. The DSCIN division specializes in complex digital and embedded systems for Artificial Intelligence (AI), High-Performance Computing (HPC) and Cyber security applications.

The focus of the LECA laboratory is the design of flexible on-chip architectures which provide high performance, energy efficiency and security. The emphasis is on secure embedded systems and AI accelerators (DNNs/CNNs). This lab is located in the Paris region (Palaiseau).

For the academic registration, the candidate will be affiliated with the Math-STIC Bretagne Oceane doctoral school of the Université Bretagne Sud university in Lorient.

Profil du candidat

Master's degree in computer science/electronics.

Good knowledge of neural networks and embedded programming.

Good analytical and experimental skills will be highly appreciated.

10/04/2025
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